Generally, an electronic circuit of a memory cell may be associated with various interface elements and signals that provide access to the memory cell. For example, a processor in a computer may utilize the interface circuitry to read data that is stored in an SRAM memory cell or to write/store data in the SRAM memory cell.
FIG. 1 schematically illustrates a traditional SRAM cell circuitry 100 utilized in an integrated circuit (IC) design. The SRAM memory cell includes interface circuitry for accessing the memory cell in order to read data stored therein or to write data in the memory cell. For example, the memory cell 100 includes a first access gate having a first transistor 101 and a second access gate having a second transistor 103 that provide access to memory cell inverter circuit 105, which can store data (e.g., zeroes and ones.) Additionally, one or more interface signals on word-line (WL) 107, a first bit-line (BL) 109, and a second BL (BLX) 111 may be utilized to access the memory cell inverter circuit 105, wherein various combinations of the interface signals can provide for various interactions/operations at the memory cell. For example, with the WL signal and pre-charged BL and BLX at a high voltage state (e.g., at logic 1), an operation of reading the memory cell content can be initiated. However, with technological advances in reduced IC node designs (e.g., scaling, smaller transistors) and lower supply voltages, the access gate transistors in a conventional SRAM design may be unable to function reliably or consistently. For instance, lower levels of supply voltage and current (i.e., ampere=I) at an SRAM cell can cause a failure of one or more functions/operations (e.g., read, write, retention, etc.) at the cell. A known approach to improve write ability is to include a write assist circuit. However write assist circuits take additional area on the chip.
A need therefore exists for methodology and circuitry enabling additional current for access gates in a memory cell without increasing supply voltage or sacrificing SRAM array area.